TIA Standards developed by committee JC-44
JEP116 - CMOS Custom Design Guidelines
JESD12 - Semicustom Integrated Circuits (Formerly Published as Standard for Gate Array Benchmark Set)
JESD12-1B - Addendum No. 1 to JESD12 - Terms and Definitions for Gate Arrays and Cell-Based Integrated Circuits
JESD12-2 - Addendum No. 2 to JESD12 - Standard for Cell-Based Integrated Circuit Benchmark Set
JESD12-3 - Addendum No. 3 to JESD12 - CMOS Gate Array Macrocell Standard
JESD12-4 - Addendum No. 4 to JESD12 - Method of Specification of Performance Parameters for CMOS Semicustom Integrated Circuits
JESD12-5 - Addendum No. 5 to JESD12 - Design for Testability Guidelines
JESD12-6 - Addendum No. 6 to JESD12 - Interface Standard for Semicustom Integrated Circuits
JESD12 - Semicustom Integrated Circuits (Formerly Published as Standard for Gate Array Benchmark Set)
JESD12-1B - Addendum No. 1 to JESD12 - Terms and Definitions for Gate Arrays and Cell-Based Integrated Circuits
JESD12-2 - Addendum No. 2 to JESD12 - Standard for Cell-Based Integrated Circuit Benchmark Set
JESD12-3 - Addendum No. 3 to JESD12 - CMOS Gate Array Macrocell Standard
JESD12-4 - Addendum No. 4 to JESD12 - Method of Specification of Performance Parameters for CMOS Semicustom Integrated Circuits
JESD12-5 - Addendum No. 5 to JESD12 - Design for Testability Guidelines
JESD12-6 - Addendum No. 6 to JESD12 - Interface Standard for Semicustom Integrated Circuits
